The present invention relates to error checking and correcting apparatus in general and, in particular, to error checking and correcting (ECC) apparatus for detecting and correcting a plurality of errors in a digital data word.
At the present time there are apparatus and methods for detecting and correcting up to two errors in a data word. To correct up to two errors in a data word, it has been the practice to provide in prior known ECC apparatus and methods syndrome word generating apparatus for generating an array of syndrome words. As distinguished from data dependent check bits, which are generated using odd and even parity techniques, syndrome words are error dependent. Consequently, when considering ECC apparatus and methods it has become conventional and convenient to consider error patterns in the data word instead of the data bits.
Considering a given error pattern in a data word with respect to any prior known array of syndrome words, it will be recognized that there is a unique syndrome word associated with each bit location in error in the data word. Heretofore, however, prior known arrays of snydrome words used for detecting and correcting a one bit error could not be used for correcting more than a one bit error in a given data word. It is, of course, highly desirable to be able to detect and correct more than one error in a given data word in certain applications. This is particularly true at the present time as technology increases the length of data fields. For a more detailed discussion of prior known ECC methods and apparatus, reference may be made to the book, Error Correcting Codes by Peterson and Weldon.